Open Verdi with existed simv

Verdi is a very useful tool in ASIC/SoC verification. We use it to check waveform and debug issues. Usually we use

to open the Verdi GUI. In this way, Verdi will compile the Design and Testbench with the files specified in dut.f and tb.f which may spend much time.

Verdi provides another way to avoid this. First you needs to add “-kdb” option when analyze your design&testbench files, re-compile and build the design&testbench, then you get the “./simv” which is an executable binary file. Now you can use below command to open verdi without re-compiling DUT/TB:

-simflow: Load the Knowledge Database (KDB) generated by VCS and use the library mapping from the synopsys_sim.setup file.

-simBin: Specify the path of the simulation binary file.

Author: aquaporcus

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